1. Technical Field
The present teaching relates to analog circuits and methods. Particularly, the present teaching relates to analog-to-digital converters (ADCs) and operating thereof
2. Discussion of Technical Background
Analog-to-digital converters (ADCs) are used for a wide range of applications, including, but not limited to, sensor interfaces, industrial applications, consumer applications, and communications. Various circuits and techniques have been developed for analog-to-digital (A/D) conversion targeting various applications and their varying requirements in terms of speed, resolution, noise, power consumption, and other performance related parameters.
FIG. 1 shows a prior-art successive-approximation-register (SAR) analog-to-digital converter (SAR ADC) 100. Successive approximation is a well-known sequential method used for A/D conversion, where an analog signal value VIN may be sampled on a capacitive digital-to-analog converter (CDAC) 101, and a sequential successive-approximation A/D conversion operation is used to generate an encoded numerical (digital) representation DOUT of the analog signal value VIN. A control circuit 102 may apply a sequence of digital codes to a plurality of input terminals 103 of CDAC 101 causing an output 104 of CDAC 101 to converge towards a predefined value (e.g., GND=0V). A comparator circuit 105 may provide an indication of a polarity of CDAC output 104. A digital control circuit 106 may use the indication of polarity to select a next digital code in the sequence of digital codes applied to CDAC input terminals 103. CDAC output 104 may represent a residue of analog signal value VIN with respect to a digital code applied to CDAC 101 incorporating a reference voltage VREF. The reference voltage may be embedded in a physical representation of a digital code. For example, a high state (logic “one”) of a bit of a digital code may be represented physically by a first reference voltage potential VH=VREF applied to an input terminal 103; likewise, a low state (logic “zero”) may be represented by applying a second reference voltage potential VL=GND=0V to the input terminal 103. Accordingly, a high/low logic value of a bit (a bit value) of a digital code may be applied to an input terminal of a CDAC by circuitry such as logic gates, switch drivers, and switches connecting the input terminal to a reference voltage circuit 107 providing a plurality of reference voltage potentials. When a residue is made to converge towards zero, a final digital code in a sequence of digital codes may be a digital representation of an analog signal value VIN. A digital circuit may combine bit values of the final digital code to provide an encoded numerical representation DOUT, which may be provided in a standardized format using standard logic levels (e.g., serial communication at 1.8V CMOS logic levels of a binary-weighted code).
A sampling node 104 of a CDAC (which is also an output 104 of CDAC 101 in FIG. 1, but a sampling node may be distinct from an output) may be coupled to a predefined potential (say ground, GND=0V) by a sampling switch 108 during an acquisition period. A charge portion may be substantially isolated on sampling node 104 at a sampling instance when sampling switch 108 is opened (i.e., when sampling switch 108 is controlled to be substantially non-conductive). By coupling an analog voltage signal VIN(t) to at least one CDAC input terminal 103 during an acquisition period, a value VIN of voltage signal VIN(t) at a sampling instance is effectively sampled on CDAC 101 (a substantially isolated charge portion is a sampled value representing VIN). Sampling switch 108 and one-or-more input switches 109 may be controlled by digital control circuit 106. An applied logic signal CNV may be used to control when to sample analog voltage signal VIN(t) and perform an A/D conversion of a sampled value VIN.
A selectable scaling of a sampled representation of an analog signal value VIN may be achieved by applying analog voltage signal VIN(t) to a selectable subset of CDAC input terminals 103 during an acquisition period. This aspect is described in U.S. Pat. No. 8,130,133, which is incorporated herein by reference for describing such scaling and the structure and operation of a prior-art successive-approximation ADC.
An input terminal of a CDAC may be assigned a weighting factor for characterizing how much a voltage variation at the input terminal affects a charge portion that may be isolated at a sampling node at a sampling instance. Weighting factors may alternately be viewed as (scaled) voltage gain factors from CDAC input terminals to a CDAC output when a sampling switch is open. For example, exemplary CDAC 101 of FIG. 1 may have four input terminals 103 with weighting factors (from left to right) w1=0.5, w2=0.25, w3=0.125, and w4=0.125. If an input voltage VIN=1.25V is applied to all four input terminals 103 at a sampling instance, a charge portion on sampling node 104 may be (−Qsamp)=C*VIN*(w1+w2+w3+w4)=C*VIN. For a 5V reference voltage (first reference potential VREF=5V; second reference potential GND=0V) an identical value for Qsamp corresponds to a digital code ‘0100’, which may alternately be described by 4 bit values b1=0, b2=1, b3=0, and b4=0. Accordingly, applying digital code ‘0100’ to exemplary CDAC 101 may cause sampling node 104 to resume a predefined potential applied to it at a sampling instance when VIN=1.25V. This property reflects that VIN/VREF=(b1*w1+b2*w2+b3*w3+b4*w4)/(w1+w2+w3+w4)=0.25. A digital code may be said to correspond to an analog signal value VIN (for a given CDAC and reference voltage), or alternately that the digital code is a representation of analog signal value VIN (the digital representation based on a reference voltage and a plurality of weighting factors).
A quantization error may depend on a resolution of a CDAC. A digital code may be said to represent an analog signal value VIN when a residue on sampling node 104 is within a predefined range corresponding to a resolution. Accordingly, a digital code may correspond to (represent) any signal value in a range, not just a specific value for which a quantization error is exactly zero. A CDAC may have a relatively high resolution (say 20 bits), and a digital code may thus correspond to any signal value in a relatively narrow range.
A numerical value representing VIN/VREF may be calculated for a CDAC when it is operated in a manner similar to that described herein, when the CDAC is characterized by a set of weighting factors, and when a digital code corresponding to VIN is known. A plurality of digital codes may be equivalent, in a sense that they all substantially correspond to a single analog signal value VIN. For example, digital code ‘0011’ is equivalent to digital code ‘0100’ with respect to exemplary CDAC 101 of FIG. 1; both digital codes represent VIN/VREF=0.25. Nominally, it does not matter which of the two codes is provided by control circuit 102 for an A/D conversion operation of VIN=1.25V.
A CDAC for which several digital codes are equivalent may provide a measure of redundancy for an A/D conversion operation. Redundancy may facilitate a control circuit to recover from certain errors that may occur during a successive-approximation ADC operation, without having to go back to a step in the operation at which such errors may have occurred. For example, over-ranging techniques exemplify a use of redundancy to facilitate an ADC to recover from some errors. Over-ranging techniques are well known and may be used in pipeline ADCs, SAR ADCs, and many other types of ADCs. Several CDAC structures that facilitate over-ranging during an A/D conversion operation are described in US Patent Application Publication US2011/0115661 A1, which is incorporated herein by reference for describing over-ranging techniques, for describing several CDAC structures, and for describing ADC circuits that may be used in combination with the present teaching.
Persons skilled in the art can analyze a CDAC structure, identify its weighting factors, and devise a method to derive a suitable encoding of a numerical value represented by a digital code corresponding to an analog signal value with respect to the CDAC. A suitable encoding may use binary-weighted digital codes to represent numerical values. Many other suitable encoding techniques are known to persons skilled in the art. An encoding technique for reducing a latency parameter is described in US Patent Application Publication US 2011/0285567 A1, which is incorporated herein by reference for describing encoding techniques and for describing over-ranging techniques. Likewise, many structures for CDACs are known in the art, including CDACs utilizing capacitive voltage division to realize very small weighting factors, and also including CDACs wherein a resistive DAC circuit structure may be used to provide scaled voltages at nodes that are capacitively coupled to a sampling node. Accordingly, a capacitive digital-to-analog converter (CDAC) shall refer to any digital-to-analog converter structure (whether or not purely capacitive) having a sampling node at which a charge portion can be substantially isolated at a sampling instance, and having a plurality of input terminals that may be substantially characterized by weighting factors. Accordingly, an analog signal value can be sampled on a CDAC, and the CDAC may be substantially characterized by weighting factors assigned to each input terminal in a plurality of input terminals. These properties characterize a general class of circuits, sampling digital-to-analog converters, which include CDACs.
An accuracy of a numerical value representing VIN/VREF derived from a digital code applied to a CDAC characterized by a set of (assumed) weighting factors depends on how accurately the assumed weighting factors used for a calculation of the numerical value represent a set of actual weighting factors of the physical CDAC structure. A difference between the assumed weighting factors and the actual weighting factors may be referred to as “mismatch of weighting factors” or “weighting factor mismatch”. Mismatch of weighting factors may (for example) be caused by mismatch of capacitor ratios in a CDAC. If assumed weighting factors are determined at design time, before a CDAC circuit is manufactured, weighting factor mismatch may be affected by manufacturing repeatability. Imperfect manufacturing repeatability of a CDAC may substantially degrade overall accuracy of an analog-to-digital converter system. A lower degree of weighting factor mismatch, and thus better overall accuracy, may be achieved by estimating (measuring) actual weighting factors of a CDAC after it has been manufactured. U.S. Pat. No. 7,705,765 describes how weighting factors of a CDAC may be measured, and how digital codes representing measured weighting factors may be stored and combined with a digital code from a A/D conversion operation to derive an encoded numerical value representing an analog signal value. U.S. Pat. No. 7,705,765 is incorporated herein by reference for describing how to measure, store, and apply codes representing weighting factors of a CDAC used in an analog-to-digital converter system, for describing over-ranging techniques, and for describing several CDAC structures and the implementation and operation of an ADC system based on successive approximation.
The circuits and methods described in U.S. Pat. No. 7,705,765 may facilitate very good estimation of CDAC weighting factors, and highly accurate ADC systems incorporating accurately estimated (assumed) weighting factors may be realized. However, a high degree of overall accuracy can be ensured only for as long as the actual weighting factors do not change substantially after the estimation process. Environmental changes (such as temperature variations) and other effects may cause some degree of weighting factor mismatch that may degrade an overall accuracy of an ADC for which weighting factors are not measured frequently. It may not be practical or desirable to interrupt an operation of an analog-to-digital converter system to measure weighting factors sufficiently frequently to ensure a long-term accurate operation.
What is needed is an analog-to-digital converter system that has a reduced sensitivity to weighting factor mismatch of a CDAC, such that highly accurate analog-to-digital converters can be implemented effectively and operated without interruption.